1. Field of the Invention
The present invention relates to a recording-system modulator for recording a digital audio signal and, more particularly, to a modulator for use on a recording/reproducing apparatus for a write-once type compact disc or a magneto-optical compact disc in controlling a digital sum variation (hereinafter referred to as a DSV) of channel coding.
2. Description of the Prior Art
It is known that, in recording data such as a digital audio signal, the digital signal is added with an error detecting/correcting code and a resultant signal is sent to a modulator to be converted into a code suitable for characteristics of a recording/reproducing system (this conversion is called channel coding).
FIG. 1(A) shows an outline of a signal format based on a compact disc (CD). For modulation, eight-to-fourteen modulation (hereinafter referred to as EFM) is used. In EFM, an input 8-bit code (hereinafter referred to as a symbol) is converted into a 14-channel-bit code, a resultant code is added with a 24-channel-bit synchronizing signal and a 14-channel-bit subcode, and the signal and the subcode are linked together with three channel margin bits to be recorded on an NRZI (Non Return to Zero Inverted) basis.
FIG. 1(B) shows a CD-based frame configuration. As shown, data consisting of 24 symbols (a music signal) and a parity consisting of eight symbols coming from a CIRC (Cross Interleave Reed-Solomon Code) encoder to the modulator in one synchronous frame (six sampled-value divisions, six samples for each of L and R channels, each sample being 16-bit data) period are each converted into blocks each consisting of 14 channel bits. These blocks are linked to each other with a pattern of three channel margin bits. The frame thus consisting of 588 channel bits is recorded on a CD at a bit rate of 4.3218 Mbps on the NRZI basis.
Each of the symbols entered in the modulator is converted into a channel bit pattern having two or more and not greater than 10 "0"s between two consecutive "1"s by referring to a look-up table ROM (Read Only Memory). A channel bit pattern of a frame synchronizing signal Sf is "100000000001000000000010". For a margin bit pattern, one of four patterns "000", "001", "010" and "100" is selected. Referring to FIG. 1(C), one subcoding frame is made up of 98 frames. For subcodes of frame 0 and frame 1, subcode synchronizing signals S.sub.0 ("00100000000001") and S.sub.1 ("00000000010010") are added respectively.
FIG. 2 shows a channel bit pattern and a DSV obtained after EFM processing with reference to a sampled value by way of example.
A 16-bit sample is divided into upper eight bits and lower eight bits, which are entered in the modulator via the CIRC encoder to be eight-to-fourteen modulated, providing information bits. As mentioned above, there are two or more and not greater than 10 "0"s between two consecutive "1"s in an information bit pattern. For the margin bits, one of "000", "001", "010" and "100" is selected. This rule is always established also at a location linking information bit patterns. Resultantly, an EFM signal on a 17-channel-bit basis (or a 27-channel-bit basis in the case of the frame synchronization signal Sf) is output from the modulator at a bit rate of 4.3218 Mbps.
Since there are two or more and not greater than 10 channel bits "0"s between two consecutive channel bits "1"s as described above, a period (or recording wavelength) of a low level or a high level of an NRZI recording waveform is always 3T or more and less than 11T as shown in FIG. 2.
In this case, a minimum recording wavelength is 3T and a maximum recording wavelength is 11T. T is one period of channel clock 4.3218 MHz. Hereinafter, this is referred to as an EFM 3T-to-11T rule.
Now, DSV (Digital Sum Variation) as an index to a DC balance of the NRZI recording waveform will be defined. The DSV is given as a time integration of a recording waveform. That is, a variation of the DSV obtained when the high level of the recording waveform continues for a unit time T is +1; the variation obtained when the low level of the recording waveform continues for the unit time T is -1.
If an initial value of the DSV at time t.sub.0 is zero, then the variation relative to the DSV time is as shown in a bottom of FIG. 2. It should be noted that a modulation signal in a period between t.sub.1 and t.sub.2 is not determined straight by 17-channel-bit pattern "01000001000001001"; rather, the modulation signal depends on a level of the signal at time t.sub.1, that is, a final level of a modulation signal waveform in a period between t.sub.0 and t.sub.1 (this level is hereinafter referred to as a CWLL).
Accordingly, the CWLL ("Current Word Last Level") of the modulation signal waveform shown is low (CWLL="0") at time t.sub.0 ; a modulation signal waveform whose CWLL="1" (high level) at time t.sub.0 has a reverse pattern with the high and low levels replaced with each other.
Likewise, the DSV depends on the CWLL for its increment and decrement. If the CWLL="0" at time t.sub.0, a variation amount of the DSV by information bit pattern "01000100100010" (hereinafter referred to as a 14NWD), or a variation amount of the DSV in a period between t.sub.0 and t.sub.0+14 is +2 as shown. Reversely, if the CWLL="1" at time t.sub.0, then the 14NWD ("Next Word DSV") is -2. A variation amount a period between t.sub.0+14 and t.sub.1+14 is referred to as a 17NWD.
Now, the margin bits to be inserted in a period between t.sub.0+14 and t.sub.1 will be described. Of the four types of margin bits "000", "001", "010" and "100", margin bits "001" and "100" cannot be inserted because of the EFM 3T-to-11T rule. Therefore, "010" or "000" is inserted. That is, let the number of "0"s in an end of an information bit pattern preceding the margin bits be B and the number of "0"s in a beginning of a current information bit pattern be A, then B=1 and A=1, so that the margin bits should start with "0" and end with "0". As a result, a margin bit pattern that can be inserted is "0X0".
Referring again to FIG. 2, the DSV obtained when "010" is inserted as the margin bits is indicated with a solid line, while the DSV obtained when "000" is inserted is indicated with a dashed line.
FIG. 3 shows a prior-art modulator having a margin bit generator. An input terminal 10 receives data with one sync frame consisting of 32 symbols from a data generator, not shown. Each 8-bit symbol is eight-to-fourteen modulated by an EFMROM 11 into 14-bit data.
Frames 0 and 1 of 98 sync frames constituting a subcoding frame are added with 14-bit subcode sync signals S.sub.0 and S.sub.1 as mentioned above. The addition of these subcode signals is performed by a subcode sync adder 12 based on a subcode sync timing signal, not shown.
A dummy frame sync adder 13 adds a 14-bit dummy frame sync signal S'f (="1XXXXXXXXXXX10") to a beginning of each sync frame based on a frame sync timing signal, not shown. A bit pattern of a start one bit and end two bits of the dummy frame sync signal S'f is the same as that of the normal 24-bit frame sync signal Sf (= "100000000001000000000010"), the margin bits can be selected in exactly the same processing in which other 14-bit data is processed.
A 14-bit data Dp including the subcode sync signals S.sub.0 and S.sub.1 and the dummy frame sync signal S'f are sequentially sent to a register 14 to be latched and upper 12 bits are sent to an inhibit margin bit decision circuit 20. At the same time, a last 14-bit data Db hitherto latched in the register 14 are output to a frame sync converter 15 and the inhibit margin bit decision circuit 20 with lower two bits stored in a register 31. Lower two bits stored last, or lower two bits of 14-bit data Dbb before the last are supplied from the register 31 to the inhibit margin bit decision circuit 20.
Current margin bits Mp supplied from a margin bit generator 40 which will be described are stored in a register 32. The 3-bit data stored last, or the margin bits Mb stored last are supplied from the register 32 to the inhibit margin bit decision circuit 20.
Based on upper 12 bits of the current 14-bit data Dp, the last 14-bit data Db, the last margin bits Mb, and the lower two bits of the 14-bit data before the last Dbb, the inhibit margin bit decision circuit 20 determines margin bits which violate the EFM 3T-to-11T rule and an exceptional inhibit rule. If violating bits are found, the decision circuit sends them to the margin bit generator 40 as an inhibit signal Sinh.
The inhibit signal Sinh consists of four bits, each of which corresponds to the four types of margin bits "100", "010", "001" and "000". For example, if the first and third margin bits "100" and "001" are inhibited by the EFM 3T-to-11T rule and the exceptional inhibit rule, the 4-bit inhibit signal Sinh is "1010".
The dummy frame sync adder 13, registers 14, 31 and 32, and inhibit margin bit decision circuit 20 constitute a decision circuit 30.
The decision circuit 30 receives the 14-bit data Dp coming from the subcode sync adder 12 and the margin bits Mp coming from the margin bit generator 40 and outputs the 14-bit data Db stored last to the frame sync converter 15 and the 4-bit inhibit signal to the margin bit generator 40 indicating that the margin bits Mp should not be used to link the last 14-bit data Db and the current 14-bit data Dp.
FIG. 4 shows an algorithm for determining inhibit margin bits. Referring to FIG. 5, the inhibit margin bit decision circuit 20 tests bits shown in shadow selected from among the input signals Dp, Db, Mb and Dbb. According to a test result, the decision circuit 20 determines the margin bits Minh not to be used for linking the last 14-bit data Db with the current 14-bit data Dp, sending the 4-bit inhibit signal Sinh to the margin bit generator 40.
In FIG. 5, an algorithm for determining the inhibit margin bit Minh by the EFM 3T-to-11T rule is as follows:
(1) If the number of "0"s in the beginning of the current 14-bit data Dp and the number of "0"s in the end of the last 14-bit data Db are eight or more in total (A+B.gtoreq.8), then the margin bit pattern "000" is inhibited (Minh="000"). PA1 (2) If a most significant bit Cl of the current 14-bit data Dp is "1" (A=0) or a next significant bit C2 is "1" (A=1) or the number of "0"s in the end of the last 14-bit data Db is nine (B=9), then the margin bit pattern "001" is inhibited (Minh="001"). PA1 (3) If the most significant bit Cl of the current 14-bit data is "1" (A=0) or a least significant bit C14 of the last 14-bit data Db is "1" (B =0), then the margin bit pattern "010" is inhibited (Minh="010"). PA1 (4) If the number of "0"s in the end of the current 14-bit data Dp is nine (A=9) or the least significant bit C14 of the last 14-bit data Db is "1" (B =0) or a next least significant bit C13 is "1" (B=1), then the margin bit pattern "100" is inhibited (Minh="100"). PA1 Case 1: the number of "0"s in the end of the last 14-bit data Db is seven and the frame sync signal is generated in a current timing. PA1 Case 2: the frame sync signal was generated previously and C1 through C6 of the current 14-bit data are "0"s (A=6). PA1 Case 3: B=7 and upper 11 bits of the Dp="10000000000". PA1 Case 4: lower 13 bits of the Db="0000000000100" and A=5. PA1 Case 5: B=6 and upper 12 bits of the Dp="010000000000". PA1 Case 6: lower 12 bits of the Db="000000000010" and A=6. PA1 Case 7: lower 11 bits of the Db="00000000001" and A=7. PA1 Case 8: the margin bit pattern last Mb="000" and Db="00000010000000" and A=1. PA1 Case 9: the least significant bit C14 of the 14-bit data before last Dbb="0" and Mb="000" and Db="00000010000000". PA1 Case 10: Mb="X00" and Db="00000000100000" and A=2. PA1 Case 11: if last two bits of Dbb="00" and Mb ="000" and Db="00000100000000", then the margin bit pattern "001" is inhibited (Minh="001"). PA1 (1) A 4-bit inhibit signal (Sinh) comes from an inhibit margin bit decision circuit. This signal sets an inhibit flag "1" to any of margin bit patterns "100", "010", "001" and "000" that violate the EFM 3T-to-11T rule and any of the margin bit patterns that generates a frame sync pattern when margin bits are added to data. PA1 (2) Following 3-bit control signals come from a DSV integrator. Each of these control signals consists of a 1-bit signal (DSVP) for indicating that cumulative DSV has a positive polarity, a 1-bit signal (ABSM) for instructing a maximum gain or a minimum gain (magnitude of power), and a 1-bit signal (DSVM) for indicating that cumulative DSV has a negative polarity. Combinations of these 1-bit signals provide following control signals for example: PA1 control signal 000: set the DSV to zero; PA1 control signal 001: direct the DSV in negative direction with minimum gain; PA1 control signal 011: direct the DSV in negative direction with maximum gain; PA1 control signal 100: direct the DSV in positive direction with minimum gain; and PA1 control signal 110: direct the DSV in positive direction with maximum gain. PA1 (3) A 1-bit signal indicating a final signal level of an NRZI waveform of 14-bit data Db preceding a margin bit pattern. When the CWLL is low, this signal is "0"; when the CWLL is high, this signal is "1". PA1 (4) A 5-bit signal for representing the DSV of 14-bit data Dp succeeding a margin bit pattern in a two's complement. PA1 (1) if 14NWD.gtoreq.4, then the 3-bit signal "100" is output from the decoder to the PLA; PA1 (2) if 14NWD=2, then the 3-bit signal "010" is output from the decoder to the PLA; PA1 (3) if 14NWD=0, then the 3-bit signal "001" is output from the decoder to the PLA; and PA1 (4) if 14NWD&lt;0, then the 3-bit signal "000" is output from the decoder to the PLA.
Referring to FIG. 6, an inhibit margin bit pattern which does not violate the EFM 3T-to-11T rule but is inhibited to prevent erroneous generation of a framing sync signal, or an inhibit margin bit pattern to be inhibited by the exceptional inhibit rule is determined as follows:
In cases 1 through 10, the margin bit pattern "000" is inhibited (Minh="000").
Referring to FIG. 33, the frame sync converter 15 converts the dummy frame sync signal S'f of sequentially entered 14-bit data into the normal 24-bit frame sync signal Sf based on the frame sync timing, not shown. The 14-bit data other than the dummy frame sync signal are supplied to a P/S (Parallel-in/Serial-out) register 16.
The 24-bit P/S register 16 alternately outputs 14-bit data (or 24-bit data for the frame sync signal Sf) and 3-bit data (margin bits) based on a channel bit clock of 4.3218 MHz.
A serial signal output from the P/S register at a rate of 4.3218 Mbps is NRZI-modulated by an NRZI circuit 17 to be supplied as an EFM signal to a recording head, not shown, or a laser diode, not shown, via a rotary transformer and a recording amplifier, not shown, for example. The EFM signal is then digitally recorded on a CD.
Upon receiving the EFM signal, a DSV integrator 60 integrates a DC component of the EFM signal in units of 17 channel bits. Based on a resultant cumulative DSV, the DSV integrator 60 outputs a 3-bit control signal to the margin bit generator 40. For example, if the cumulative DSV is positive in polarity, the bit pattern "001" instructing decrement (-) of the cumulative DSV is output as the control signal. If the cumulative DSV is zero, the bit pattern "010" instructing balance (0) of the cumulative DSV is output. If the cumulative DSV is negative in polarity, the bit pattern "100" instructing increment (+) of the cumulative DSV is output.
Referring again to FIG. 4, the margin bit generator 40 operates as follows. This circuit outputs a most suitable margin bit pattern of the four types the margin bit patterns "100", "010", "001" and "000". The most suitable bit pattern denotes that, when the two pieces of 14-bit data Db and Dp are linked together with this margin bit pattern, the EFM 3T-to-11T rule is also established at the link, no erroneous generation of the frame sync signal occurs, and the cumulative DSV of the EFM signal converges to zero.
The margin bit generator 40 does not test each margin bit pattern individually for determining the most suitable one; rather, this circuit determines the most suitable pattern from the beginning based on conditions such as the bit patterns of the two pieces of 14-bit data and the cumulative DSV. Input signals to the margin bit generator 40 are as follows.
First, a 4-bit inhibit signal Sinh comes from the inhibit margin bit decision circuit 20. If a margin bit pattern violating the EFM 3T-to-11T rule is found or a margin bit pattern which cannot be inserted between the two pieces of 14-bit data Db and Dp because the pattern will erroneously generate the frame sync signal is found, such a pattern is disabled by setting a bit of the inhibit signal corresponding to the margin bit to "1". For example, of the four margin bit patterns "100", "010", "001" and "000", if the first and third patterns are disabled, the 4-bit inhibit signal will be "1010".
Next, a 3-bit control signal is entered in the margin bit generator 40 from the DSV integrator 60 according to the cumulative DSV. This 3-bit control signal indicates, from the most significant bit to the least significant bit, that a desired control direction of the cumulative DSV is increment (+), balance (0), and decrement (-). Accordingly, if the cumulative DSV is greater than zero, this control signal is "001" to instruct decrement of the cumulative DSV; if the cumulative DSV is smaller than zero, the control signal is "100" to instruct increment of the cumulative DSV; and if the cumulative DSV is equal to zero, the control signal is "010" to instruct to balance the cumulative DSV as far as possible.
Then, a 5-bit 14NWD signal and a 1-bit CWLL signal are entered in the margin bit generator 40.
FIG. 7 shows an example of NRZI waveforms of the two pieces of 14-bit data Db and Dp to be linked together by the margin bits.
A variation of the cumulative DSV caused by adding the margin bits to the last 14-bit data Db, or a DC component of the margin bits (hereinafter referred to as the DSV of the margin bits) is represented with reference to a low level ("0") of a signal level, or the CWLL of an NRZI waveform at a start of the margin bits.
That is, as shown in FIGS. 7(A) through (D), the DSV of the first margin bit pattern "100" is +3, that of the second margin bit pattern "010" is +1, that of the third margin bit pattern "001" is -1, and that of the fourth margin bit pattern "000" is -3. If the CWLL ="1" (high level), the signs of these DSV values are inverted.
Likewise, a variation of the cumulative DSV caused by adding the current 14-bit data Dp, or a DC component, or the 14 NWD of the 14-bit data Dp is represented with reference to a low level of a signal level of an NRZI waveform at a start of the 14-bit data Dp. That is, the 14NWD of the 14-bit data Dp (="00100100000100") is -2.
A variation of the cumulative DSV caused by linking the 14-bit data Db with following 14-bit data Dp by using 3-bit margin bit pattern, or the 17NWD is obtained by subtracting the 14NWD from the DSV of margin bits for the first, second or third margin bit pattern; for the fourth margin bit pattern ("000"), the variation is obtained by adding the 14NWD to the DSV of margin bits.
FIG. 8 shows a monograph for obtaining the 17NWD from the 14NWD when the CWLL="0" (low level). FIG. 9 shows a monograph for obtaining the 17NWD from the 14NWD when the CWLL="1".
In FIG. 8, each of (A), (B), (C) and (D) indicates the 17NWD corresponding to each of the four margin bit patters "100", "010", "001" and "000" to be inserted.
Now, referring to FIG. 8, a case in which the 14NWD of next 14-bit data Dp is 3 or more for example will be considered.
First, if the cumulative DSV so far is zero or negative in value, a next 17NWD is made zero or positive in value to increment the cumulative DSV toward zero. In the case of 14NWD.gtoreq.3, a margin bit pattern that provides 17NWD.gtoreq.0 is only "000". Therefore, this bit pattern is given a first priority.
If the EFM 3T-to-11T rule or the exceptional inhibit rule prevents insertion of the margin bit pattern of the first priority "000" then the margin bit pattern "100" is given a second priority, the margin bit pattern "101" is given a third priority, and the margin bit pattern "001" is given a fourth priority. Thus, even if CWLL=0, the most suitable margin bit pattern in the case where the 14NWD.gtoreq.3 can be determined straightforwardly. This makes it unnecessary to test all of the four margin bit patterns individually.
Likewise, if the 14NWD.gtoreq.3 and the cumulative DSV so far is positive in value, the next 17NWD is made negative to decrement the cumulative DSV. In this case, the margin bit patterns "010", "001", "100" and "000" are prioritized in this order, the most suitable margin bit pattern can be determined straightforwardly.
Similarly, for each of cases where 14NWD=2, 14NWD=1, 14NWD=0 and 14NWD.gtoreq.-1, the four types of the margin bit patterns are prioritized logically.
Referring to FIG. 9, where CWLL="1" (high level), the margin bit patterns are prioritized for each of five cases in which the 14NWD of the next 14-bit data Dp is +3 or more, +2, +1, 0 and -1 or less. However, as is clearly seen from comparison between CWLL="0" of FIG. 8 and CWLL="1" of FIG. 9, both flags are symmetrical to each other with an x-axis (indicating the 14NWD) in between. Therefore, inverting a sign of an y-axis (indicating the 17NWD) makes the monograph of FIG. 9 be the same as the monograph of FIG. 8. That is, if CWLL="1", converting the 3-bit control signal from "100" (incrementing the cumulative DSV) to "001" (decrementing the cumulative DSV) or from "001" to "100" allows to apply the algorithm of determining the most suitable margin bit pattern in the case where CWLL="1" without change.
In the margin bit generator 40 of FIG. 4, reference numeral 41 represents a decoder which decodes the 3-bit control signal with the CWLL signals used as gate signals. A truth table of the decoding is shown in FIG. 10(A).
Reference numeral 42 represents a decoder for converting the 14NWD represented in a 5-bit two's complement to a 4-bit signal indicating the above-mentioned five cases. A truth table of the decoding is shown in FIG. 10(B).
Reference numeral 43 represents a programmable logic array (PLA) programmed so that it receives the 4-bit inhibit signal from the inhibit margin bit decision circuit 20, the 3-bit control signal from the decoder 41, and 4-bit signal from the decoder 42 to output a most suitable margin bit pattern 44. Of truth tables programmed in the PLA 43, 52-term truth tables obtained when CWLL="0" are shown in FIGS. 11(A) and 11(B).
In FIGS. 11(A) and 11(B), "1" indicates a condition established and "0" indicates a condition not established "X" indicates "don't care, " that is, a condition may be or may not be established. For example, top four rows (terms) of the truth table of FIG. 11(A) denote as follows.
If CWLL=0 and the control signal="XX0" (at least not a decrement instruction), and if 14NWD.gtoreq.3, then the margin bit patterns "000", "100", "010" and "001" are prioritized in this order. That is, if the margin bit pattern "000" of the first priority is not inhibited (the inhibit signal="XXX0"), this pattern is output as the most suitable margin bit pattern. If the margin bit pattern "000" of the first priority is inhibited and the margin bit pattern "100" of the second priority is not inhibited (the inhibit signal="XX01"), then the margin bit pattern "100" of the second priority is output as the most suitable margin bit pattern.
If both the margin bit patterns of the first and second priorities are inhibited and the margin bit pattern of the third priority is not inhibited (the inhibit signal="X011"), then the margin bit pattern ("010") of the third priority is output as the most suitable margin bit pattern. If all of the margin bit patterns of the first, second and third priorities are inhibited (the inhibit signal="0111"), then the margin bit "001" of the fourth priority is output.
Thus, without testing each margin bit pattern individually, the most suitable margin bit pattern 44 logically determined by the PLA 43 is output.
Consequently, the conventional modulator controls the margin bit patterns only based on the DSV polarities by a certain gain without monitoring a DSV absolute value. This causes a poor convergence when the DSV absolute value is large. When the DSV absolute value is small, an extra gain is added to make the DSV unstable.
On the other hand, an amplitude of a signal read from a disc on a mini-disc system is as small as about 1/30 of that of a signal read from a full-size compact disc, requiring proper control of the DSV. This requirement has not been fully satisfied due to the above-mentioned problem.